| 大会名称 |
|---|
| 2009年 情報科学技術フォーラム(FIT) |
| 大会コ－ド |
| F |
| 開催年 |
| 2009 |
| 発行日 |
| 2009/8/20 |
| セッション番号 |
| 2C |
| セッション名 |
| アクセラレータ |
| 講演日 |
| 2009/09/02 |
| 講演場所(会議室等) |
| C会場（9号館1F 913教室） |
| 講演番号 |
| RC-004 |
| タイトル |
| 三次元アレイプロセッサ構造を用いた効率的な3D-DCT計算機構の提案 |
| 著者名 |
| 生垣 佑樹, 武石 直人, 宮崎 敏明, Sedukhin Stanislav G., |
| キーワード |
| 3D-DCT, アレイプロセッサ, トーラス, FPGA, パラレルI/O |
| 抄録 |
| Traditional array processors randomly access to input/coefficient data stored in memory many times during the three dimensional discrete cosine transform (3D-DCT) calculation. Hence, it becomes a bottleneck of fast calculation. In this paper, a three dimensional array processor dedicated to 3D-DCT is proposed. The array processor tremendously reduces the data swapping or replacement during the calculation. Thus, it contributes to the performance improvement. The computational complexity of the proposed array processor is O(N) for an N×N×N input data cube while that of the 3D-DCT direct calculation is O(N4). A specified I/O architecture and throughput/cost-effective architectures are also discussed for practical implementation. Experimental results of an FPGA (Field Programmable Gate Array) implementation show that our architecture is not only low-power consumption but cost effective. |
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