| 大会名称 |
|---|
| 2009年 情報科学技術フォーラム(FIT) |
| 大会コ－ド |
| F |
| 開催年 |
| 2009 |
| 発行日 |
| 2009/8/20 |
| セッション番号 |
| 7B |
| セッション名 |
| アーキテクチャ |
| 講演日 |
| 2009/09/04 |
| 講演場所(会議室等) |
| B会場（9号館1F 912教室） |
| 講演番号 |
| RC-002 |
| タイトル |
| Reducing Branch Misprediction Penalty in Superscalar Microprocessors by Recovering Critical Misprediction |
| 著者名 |
| 叶 炯耀, 万 宇, 董 宜平, 鮑 治国, 渡邊 孝博, |
| キーワード |
| branch msiprediction, ciricial path, trace cache, recovery mechanism |
| 抄録 |
|
In modern superscalar processor, branch misprediction penalty becomes a critical factor in overall processor performance, especially in deeply pipelined processors. The branch misprediction penalties include branch resolution time and refill the pipeline. A large number of aggressive schemes (e.g. checkpoint scheme) are widely used in most of current approaches to reduce the branch resolution time. However, current recovery mechanisms still implicitly reduce the Instruction Per Cycle (IPC) because the mispredicted instructions saved in the front-end stages must be flushed, and then the instructions from correct path are restarted from fetch stage. In this paper, we propose a recovery mechanism, called Recovery Critical Misprediction (RCM), to reduce the branch misprediction penalty due to re-fill and flush. The mechanism uses a Simplicity Trace Cache (STC) to trace mispredicted instructions that are enough critical, and selectively forks a second path from STC following a conditional branch instruction. Upon a misprediction, the processor can immediately starts issuing correct instructions from the alternate path. Experimental results employing SPECint 2000 benchmark show that, using a processor with RCM, IPC value is significantly improved by 10.7% on average compared with a conventional processor without RCM. |
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