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An FPGA is easy-to-use for manufacturing due to its merits, i.e., designed for performance, time to market, low cost, high reliability, and long-term maintenance. But, by the increasing of FPGA size and the deep-submicron process technology, the power consumption of FPGA limits its application in mobile products. So, many low power methods and FPGA architectures have been researched. In this paper, a novel FPGA architecture with sophisticated power-gating is proposed. Each Logic Element (LE) or Clustered Logic Block (CLB) in FPGA could be powered off separately by the status of some internal logic signals. So, this method could dynamically save the power of LEs or CLBs which are unused in the circuit after download or entering sleep mode without any control signals out of FPGA. For this advantage, our proposed method is very useful in reducing FPGA leakage power especially when used as commercial mobile chips. Moreover, it will not only reduce the FPGA leakage, but also can be used for the emulation of ASIC chips before tape-out.
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