| 大会名称 |
|---|
| 2019年 ソサイエティ大会 |
| 大会コ－ド |
| 2019S |
| 開催年 |
| 2019 |
| 発行日 |
| 2019/8/27 |
| セッション番号 |
| A-1 |
| セッション名 |
| 回路とシステム |
| 講演日 |
| 2019/9/10 |
| 講演場所(会議室等) |
| C棟 2F Ｃ203講義室 |
| 講演番号 |
| A-1-7 |
| タイトル |
| A design of arithmetic unit based on self-synchronous circuit |
| 著者名 |
| ○Di Cui, Makoto Ikeda, |
| キーワード |
| self synchronous |
| 抄録 |
| In this study, we focus on using the dual-pipeline self-synchronous circuit to design a 8 bit ripple carry adder. The self synchronous circuit is designed in the architecture called DCVSL and can operate at gate-level pipeline stage.The whole circuit is controlled by the Completion Detection (CD) signal generated by each stage of self synchronous logic gate.It can achieve about 2 times throughput compared with previous research in dynamic logic fast adder design. |
| 本文pdf |
|
PDF download
|