| 大会名称 |
| 2017年 総合大会 |
| 大会コ－ド |
| 2017G |
| 開催年 |
|
2017
|
| 発行日 |
|
|
| セッション番号 |
|
C-12
|
| セッション名 |
|
集積回路
|
| 講演日 |
|
2017/3/25
|
| 講演場所(会議室等) |
|
共通講義棟南 403
|
| 講演番号 |
|
C-12-16
|
| タイトル |
|
A Synthesizable High Resolution Linear DTC
|
| 著者名 |
|
◎Haosheng Zhang, Kenichi Okada, Akira Matsuzawa,
|
| キーワード |
|
synthesizable, resolution, linear, DTC
|
| 抄録 |
|
The basic element of a DTC is a variable delay element. In term of fully synthesis, one straightforward way is to use a long delay chain. However, the resolution is severely limited by the technology, around 20ps in TSMC 65n CMOS technology. Also the linearity is not ensured when a sub-picosecond resolution is required after automatic synthesis.In this research, a high resolution DTC architecture suitable for synthesis based on the concept of constant slope DTC is proposed. It maintains a high linearity even a sub-picosecond is required, and the resolution is kind free of technology limitation.
|
| 本文pdf |
|
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|
