| 大会名称 |
| 2017年 総合大会 |
| 大会コ－ド |
| 2017G |
| 開催年 |
|
2017
|
| 発行日 |
|
|
| セッション番号 |
|
C-12
|
| セッション名 |
|
集積回路
|
| 講演日 |
|
2017/3/24
|
| 講演場所(会議室等) |
|
共通講義棟南 402
|
| 講演番号 |
|
C-12-1
|
| タイトル |
|
A Study of Injection-locking PLL Phase Calibration with Symmetrical Phase Detector and Multiplexer
|
| 著者名 |
|
◎Bangan Liu, Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa,
|
| キーワード |
|
PLL, injection-locking, synthesizable
|
| 抄録 |
|
As CMOS process scales, ring oscillator based all-digital injection-locking PLL(IL-PLL) is a promising solution to frequency synthesis applications. However the jitter performance of IL-PLL depends on the frequency difference between digitally controlled oscillator(DCO) free-run frequency and the target output frequency. This work presents a phase calibration method that continuously tracking frequency across PVT variations.
|
| 本文pdf |
|
PDF download
|
