IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2012/09/11)

Presentation

表紙

[Date]2012/9/11
[Paper #]

FPGA-based video stabilisation

Toru YABUKI, Yoshiki YAMAGUCHI, Yuetsu KODAMA,

[Date]2012/9/11
[Paper #]RECONF2012-24

A Development of Traffic-Sign Detection System by Using Vector Processor Venice

Yoshiya SUGITA, Tomoki TOMISAWA, Masahiro FUKUI,

[Date]2012/9/11
[Paper #]RECONF2012-25

JPEG encoder design improvement and its evaluation for Dynamic Reconfigurable Circuit

Hajime SAWANO, Nobuyuki ARAKI, Takashi KAMBE,

[Date]2012/9/11
[Paper #]RECONF2012-26

An approach for generating new timbres by the use of an FPGA

Suguru OCHIAI, Yoshiki YAMAGUCHI, Yuetsu KODAMA,

[Date]2012/9/11
[Paper #]RECONF2012-27

An Implementation and Evaluation of SOC Estimation System for Lithium-ion Battery by PSoC

Masashi FUJIMOTO, Tatsuya INOUE, Lei LIN, Masahiro FUKUI,

[Date]2012/9/11
[Paper #]RECONF2012-28

The LSI Design Methodology of Tamper Resistant Cryptographic Circuit

Takeshi FUJINO, Mitsuru SHIOZAKI, Takaya KUBOTA, Masaya Yoshikawa,

[Date]2012/9/11
[Paper #]RECONF2012-29

Area-Efficient Design of Asynchronous Circuits Based on Balsa Framework for Synchronous FPGAs

Masanori HARIYAMA, Yoshiya KOMATSU, Michitaka KAMEYAMA,

[Date]2012/9/11
[Paper #]RECONF2012-30

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

Masanori HARIYAMA, Yoshiya KOMATSU, Michitaka KAMEYAMA,

[Date]2012/9/11
[Paper #]RECONF2012-31

An Area Minimized Logic Cluster using COGRE Logic Cell

Toshiya TAKAHASHI, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI,

[Date]2012/9/11
[Paper #]RECONF2012-32

Castle of Chips : A reconfigurable technique for multiple chips implementation

Hideharu AMANO,

[Date]2012/9/11
[Paper #]RECONF2012-33

Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA

Kunihiro UEDA, Naoki KAWAMOTO, Keisuke DOHI, Yuichiro SHIBATA, Kiyoshi OGURI,

[Date]2012/9/11
[Paper #]RECONF2012-34

Superimposing configuration acceleration method of an optically : reconfigurable gate array including a speed adjustment bit

Takashi YOZA, Minoru WATANABE,

[Date]2012/9/11
[Paper #]RECONF2012-35

Effects of Power Saving by Dynamic Partial Reconfiguration in Video Shape Detection Processing

Naoki KAWAMOTO, Kunihiro UEDA, Keisuke DOHI, Yuichiro SHIBATA, Kiyoshi OGURI,

[Date]2012/9/11
[Paper #]RECONF2012-36

Fast Flaw Detection of Liquid Glass with a FPGA Board

Keisuke MATSUYAMA, Meng LIN, Yasuo TENJO, Katsuhiro YAMAZAKI,

[Date]2012/9/11
[Paper #]RECONF2012-37

Gray-level image detection of a dynamically reconfigurable vision-chip architecture

Yuki KAMIKUBO, Minoru WATANABE, Shoji KAWAHITO,

[Date]2012/9/11
[Paper #]RECONF2012-38

Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2-D FDTD Computation

Masanori HARIYAMA, Muthumalawaidyasoority HASITHA, Yasuhiro TAKEI, Michitaka KAMEYAMA,

[Date]2012/9/11
[Paper #]RECONF2012-39

Prototyping Tightly-Coupled FPGA Cluster for Lattice Boltzmann Computation

Kentaro SANO, Yoshiaki KONO, Hayato SUZUKI, Ryotaro CHIBA, Satoru YAMAMOTO,

[Date]2012/9/11
[Paper #]RECONF2012-40

A Design Framework for Reconfigurable IPs with VLSI CADs

Qian ZHAO, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI,

[Date]2012/9/11
[Paper #]RECONF2012-41