| Presentation | 2012-09-18 The LSI Design Methodology of Tamper Resistant Cryptographic Circuit Takeshi FUJINO, Mitsuru SHIOZAKI, Takaya KUBOTA, Masaya Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Tamper LSI Design Methodology have to be applied in order to implement secure cryptographic circuit which is resistant to side-channel attack such as DPA(Differential Power Analysis). The principle of DPA, some typical countermeasures against DPA, and the problem on the LSI implementation are introduced in this paper. The "dual-rail RSL memory" which consumes constant power irrespective of input/output value, is developed. The cryptographic design methodology, in which the "dual-rail RSL memory" is used on a non-linear circuit, and the additive masked logic using XOR gate is used on a linear circuit, is easy to be implemented on SoC, because these methods are easy to be implemented in the conventional LSI design flow. The AES cryptographic circuit, which is the most popular cryptographic algolithm, was designed in O.18 um CMOS technology. The test chip demonstrates the high tamper resistance against power analysis. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Tamper Resistant LSI / Side-Channel Attack / AES / DPA / CPA / WDDL / RSL / Dual-rail RSL Memory |
| Paper # | RECONF2012-29 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2012/9/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The LSI Design Methodology of Tamper Resistant Cryptographic Circuit |
| Sub Title (in English) | |
| Keyword(1) | Tamper Resistant LSI |
| Keyword(2) | Side-Channel Attack |
| Keyword(3) | AES |
| Keyword(4) | DPA |
| Keyword(5) | CPA |
| Keyword(6) | WDDL |
| Keyword(7) | RSL |
| Keyword(8) | Dual-rail RSL Memory |
| 1st Author's Name | Takeshi FUJINO |
| 1st Author's Affiliation | Faculty of Science and Engineering Ritsumeikan University() |
| 2nd Author's Name | Mitsuru SHIOZAKI |
| 2nd Author's Affiliation | Research Organization of Science and Engineering Ritsumeikan University |
| 3rd Author's Name | Takaya KUBOTA |
| 3rd Author's Affiliation | Research Organization of Science and Engineering Ritsumeikan University |
| 4th Author's Name | Masaya Yoshikawa |
| 4th Author's Affiliation | Faculty of Science and Engineering Meij o University |
| Date | 2012-09-18 |
| Paper # | RECONF2012-29 |
| Volume (vol) | vol.112 |
| Number (no) | 203 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |