Presentation | 2012-09-18 Superimposing configuration acceleration method of an optically : reconfigurable gate array including a speed adjustment bit Takashi YOZA, Minoru WATANABE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In recent years, demand fbr realizing robust embedded devises used in space is increasing daily. Under a space environment, embedded devices suffer from many high-energy charged particles. Therefore, we have been developing optically reconfigurable gate arrays (ORGAs) which are very robust against such high-energy charged particles. Up to now, we have demonstrated that a configuration speed adjustment method can optimize each reconfiguration speed of ORGAs. However, we have never confirmed whether the method can function correctly when configuration contexts are superimposed. Therefor, this paper demonstrates that the superimposing configuration acceleration method including a speed adjustment bit can be used. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Optically reconfigurable gate arrays / FPGAs / Holographic memories / Fault tolerance |
Paper # | RECONF2012-35 |
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Committee | RECONF |
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Conference Date | 2012/9/11(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Superimposing configuration acceleration method of an optically : reconfigurable gate array including a speed adjustment bit |
Sub Title (in English) | |
Keyword(1) | Optically reconfigurable gate arrays |
Keyword(2) | FPGAs |
Keyword(3) | Holographic memories |
Keyword(4) | Fault tolerance |
1st Author's Name | Takashi YOZA |
1st Author's Affiliation | Shizuoka University() |
2nd Author's Name | Minoru WATANABE |
2nd Author's Affiliation | Shizuoka University |
Date | 2012-09-18 |
Paper # | RECONF2012-35 |
Volume (vol) | vol.112 |
Number (no) | 203 |
Page | pp.pp.- |
#Pages | 5 |
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