Presentation 2012-09-18
An Area Minimized Logic Cluster using COGRE Logic Cell
Toshiya TAKAHASHI, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI,
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Abstract(in English) These days, FPGAs (Field Programmable Gate Arrays) is required to increase in size and performance in order to deal with complicated systems. To increase in size and performance of FPGAs, we proposed two ideas in previous work The first is a small-memory logic cell;COGRE (Compactly Organized Generic Reconfigurable Element),the second is the method of input-sharing between BLEs(Basic Logic Elements).In this paper, we propose a new approach to combine these two ideas. The experimental results show that the product of area and delay of our proposed logic block is 42% smaller than that of the traditional one. Further, we find out that our proposed logic block is quite high perfbrmance as compared with the COGRE based logic block
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Keyword(in English) logic block / COGRE / local interconnect
Paper # RECONF2012-32
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Conference Information
Committee RECONF
Conference Date 2012/9/11(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Area Minimized Logic Cluster using COGRE Logic Cell
Sub Title (in English)
Keyword(1) logic block
Keyword(2) COGRE
Keyword(3) local interconnect
1st Author's Name Toshiya TAKAHASHI
1st Author's Affiliation Graduate School of Science and Technology Kumamoto University()
2nd Author's Name Kazuki INOUE
2nd Author's Affiliation Graduate School of Science and Technology Kumamoto University
3rd Author's Name Motoki AMAGASAKI
3rd Author's Affiliation Graduate School of Science and Technology Kumamoto University
4th Author's Name Masahiro IIDA
4th Author's Affiliation Graduate School of Science and Technology Kumamoto University
5th Author's Name Morihiro KUGA
5th Author's Affiliation Graduate School of Science and Technology Kumamoto University
6th Author's Name Toshinori SUEYOSHI
6th Author's Affiliation Graduate School of Science and Technology Kumamoto University
Date 2012-09-18
Paper # RECONF2012-32
Volume (vol) vol.112
Number (no) 203
Page pp.pp.-
#Pages 6
Date of Issue