Presentation | 2012-09-18 JPEG encoder design improvement and its evaluation for Dynamic Reconfigurable Circuit Hajime SAWANO, Nobuyuki ARAKI, Takashi KAMBE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Reconfigurable Computing(RC) has been proposed as a new paradigm to address the conflicting design requirements of high performance and area efficiency. This paper, proposes acceleration and reduction of circuit scale of JPEG Eecoder using "Dynamically Reconfigurable Processor"and evaluates its performance. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Dynamic reconfigurable circuit / DAPDNA-2 / PE-based pipelining / JPEG encoder |
Paper # | RECONF2012-26 |
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Conference Information | |
Committee | RECONF |
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Conference Date | 2012/9/11(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | JPEG encoder design improvement and its evaluation for Dynamic Reconfigurable Circuit |
Sub Title (in English) | |
Keyword(1) | Dynamic reconfigurable circuit |
Keyword(2) | DAPDNA-2 |
Keyword(3) | PE-based pipelining |
Keyword(4) | JPEG encoder |
1st Author's Name | Hajime SAWANO |
1st Author's Affiliation | Graduate School of Science and Engineering Kinki University() |
2nd Author's Name | Nobuyuki ARAKI |
2nd Author's Affiliation | Graduate School of Science and Engineering Kinki University |
3rd Author's Name | Takashi KAMBE |
3rd Author's Affiliation | School of Science and Engineering Kinki University |
Date | 2012-09-18 |
Paper # | RECONF2012-26 |
Volume (vol) | vol.112 |
Number (no) | 203 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |