| Presentation | 2012-09-18 Castle of Chips : A reconfigurable technique for multiple chips implementation Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The number of stacked chips with wireless inductive coupling interconnect is limited by the physical space for bonding wires of supply voltage. A new chip stacking structure called CoC(Castle on Chips)is proposed for stacking a large number of chips without chip-to-chip wired interconnection. In the CoC, each chip has at least two sets of inductors, and is stacked on two chips in the lower layer shifting in the half chip size. Each chip takes a role of bridge of two chips in the lower layer and two in the upper layer. As examples of the CoC, linear structure and circular structure are proposed. They form stairway boundary mesh structure, and a simple extension of Dimension Order Routing(DOR)can be deadlock free if enough number of chips is stacked. The average distance of stairway boundary mesh is better than that of rectangular mesh, and sometimes comparable that of squire mesh. The circular stacking is advantageous when the number of stacking layers is strictly limited. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Inductive coupling interconnect / Interconnection Network / Chip level reconfiguration |
| Paper # | RECONF2012-33 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2012/9/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Castle of Chips : A reconfigurable technique for multiple chips implementation |
| Sub Title (in English) | |
| Keyword(1) | Inductive coupling interconnect |
| Keyword(2) | Interconnection Network |
| Keyword(3) | Chip level reconfiguration |
| 1st Author's Name | Hideharu AMANO |
| 1st Author's Affiliation | Graduate School of Science and Technology Keio University() |
| Date | 2012-09-18 |
| Paper # | RECONF2012-33 |
| Volume (vol) | vol.112 |
| Number (no) | 203 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |