number | title/author |
---|---|
D2-1 | Efficient FPGA-based Hardware Algorithms for Approximate String Matching Sadatoshi Mikami, Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama, |
D2-2 | Design and Analysis of On-chip Leakage Monitor using an MTCMOS circuit Satoshi Koyama, Seidai Takeda, Kimiyoshi Usami, |
D2-3 | A Multi-thread Processor Architecture With Dual Phase Variable-Length Instructions HyungKi Jeong, KwangYeob Lee, Jae-Chang Kwak, |
D2-4 | Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages Yusuke Umahashi, Yuki Kambayashi, Masaru Kato, Yohei Hasegawa, Hideharu Amano, Kimiyoshi Usami, |
D2-5 | Power-Switch Clustering Method for Static Timing Analysis Tatsunori Hashida, Kimiyoshi Usami, |