number | title/author |
---|---|
D1-1 | High-Performance Architecture of Transform Circuit for Multi-standard Video CODEC Seonyoung Lee, Kyeongsoon Cho, |
D1-2 | A New Implementation of Multilevel Framework for Interconnect-Driven Floorplanning Zheng Xu, Song Chen, Takeshi Yoshimura, Yong Fang, |
D1-3 | Design of Application Specific Processor and Compiler for H.264 CAVLC Decoding Jae-Jin Lee, Jun-Young Lee, MooKyoung Jeong, SeongMo Park, NakWoong Eum, |
D1-4 | A Power-Saving 1GBPS Irregular LDPC Decoder based on High-Efficiency Message-Passing Wenming Tang, Wen Ji, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto, |
D1-5 | A Design Method of Finding Optimal Sampling Pulses and Transistor Sizes in a Sampling Circuit for Liquid Crystal Displays Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa, |