Information and Systems-Dependable Computing(Date:2004/02/13)

Presentation
表紙

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[Date]2004/2/13
[Paper #]
目次

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[Date]2004/2/13
[Paper #]
Diagnosis for Open Faults Based on Detecting/Un-detecting Information on Tests

Yuichi SATO,  Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Yuzo TAKAMATSU,  

[Date]2004/2/13
[Paper #]DC2003-90
Diagnosis for Single/Multiple Stuck-at Faults by Ambiguous Diagnostic Test Set

Yukihiro YAMAMOTO,  Hidekazu AYANO,  Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Yuzo TAKAMATSU,  

[Date]2004/2/13
[Paper #]DC2003-91
The Relationship Between the Test Properties and the Fault Models in Diagnosis of Single Bridging Faults by Using Pass/Fail Information

Koji YAMAZAKI,  Yuzo TAKAMATSU,  

[Date]2004/2/13
[Paper #]DC2003-92
Analog LSI Relation Among Measurement Accuracy, Yield, and Test Time

Hideo KOHlNATA,  

[Date]2004/2/13
[Paper #]DC2003-93
Proposal of Low Power Board-Type Reconfigurable Tester

Masayuki Sato,  Hiroyuki Itabashi,  Nobuyuki Otsuka,  Yasuro Kobayashi,  Osamu Muto,  Masayuki AraI,  Satoshi Fukumoto,  Kazuhiko Iwasaki,  Koji Uehara,  Isao Shimizu,  Haruo Mamyouda,  

[Date]2004/2/13
[Paper #]DC2003-94
Dataflow Oriented Template Generation for Instruction-Based Self-Test of Processor Cores

kazuko KAMBE,  Michiko INOUE,  Hideo FUJlWARA,  

[Date]2004/2/13
[Paper #]DC2003-95
Input Temporal Spatial Constraint of Controller for Instruction-Based Self-Testing of Processor Cores

Naotaka HOASHI,  Kazuko KAMBE,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2004/2/13
[Paper #]DC2003-96
A Test Vector Ordering for Overhead Reduction of Test Decompressors

Masakuni OCHI,  Michihiro SHINTANI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2004/2/13
[Paper #]DC2003-97
Random Access Scan : A solution to test power, test data volume and test time

Dong Hyun BAIK,  Kewal K. SALUJA,  Seiji KAJIHARA,  

[Date]2004/2/13
[Paper #]DC2003-98
Power-Conscious Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability

Hisakazu TAKAKUWA,  Tomokazu YONEDA,  Hideo FUJIWARA,  

[Date]2004/2/13
[Paper #]DC2003-99
A DFT Selection Method for Reducing Test Application Time of System-on-Chips

Masahide MIYAZAKI,  Toshinori HOSOKAWA,  Hiroshi DATE,  Michiaki MURAOKA,  Hideo FUJIWARA,  

[Date]2004/2/13
[Paper #]DC2003-100
Classification of Sequential Circuits Based on Combinational Test Generation Complexity

Chia Yee OOI,  Hideo FUJIWARA,  

[Date]2004/2/13
[Paper #]DC2003-101
Majority Voting by Partial Retries

Mamoru OHARA,  Masayuki ARAI,  Satoshi FUKUMOTO,  Kazuhiko IWASAKI,  

[Date]2004/2/13
[Paper #]DC2003-102
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[Date]2004/2/13
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[Date]2004/2/13
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