| Presentation | 2004/2/13 Power-Conscious Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability Hisakazu TAKAKUWA, Tomokazu YONEDA, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a design-for-testability method that transforms a given SoC into consecutively testable one under power constraint. The proposed method can deal with various types of cores: P1500 wrapped cores, unwrapped scan cores, unwrapped non-scan cores and BISTed cores. When an SoC and a user defined importance ratio between area overhead and test application time are given, the proposed method can create TAM and test schedule that meet the importance ratio with low computational cost by using some heuristics. Moreover, the proposed method can achieve low area overhead not only by adding test buses but also by utilizing existing interconnects and consecutive transparency of cores as a part of TAM. Experimental results show the advantages of the proposed method compared to test bus architecture, which is a well known TAM design, and our previous method based on consecutive testability of SoC. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | system-on-a-chip / design for testability / test access mechanism / test scheduling / power consumption / consecutive testability / Co-optimization |
| Paper # | DC2003-99 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2004/2/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power-Conscious Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability |
| Sub Title (in English) | |
| Keyword(1) | system-on-a-chip |
| Keyword(2) | design for testability |
| Keyword(3) | test access mechanism |
| Keyword(4) | test scheduling |
| Keyword(5) | power consumption |
| Keyword(6) | consecutive testability |
| Keyword(7) | Co-optimization |
| 1st Author's Name | Hisakazu TAKAKUWA |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City() |
| 2nd Author's Name | Tomokazu YONEDA |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City |
| Date | 2004/2/13 |
| Paper # | DC2003-99 |
| Volume (vol) | vol.103 |
| Number (no) | 668 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |