Presentation | 2004/2/13 Proposal of Low Power Board-Type Reconfigurable Tester Masayuki Sato, Hiroyuki Itabashi, Nobuyuki Otsuka, Yasuro Kobayashi, Osamu Muto, Masayuki AraI, Satoshi Fukumoto, Kazuhiko Iwasaki, Koji Uehara, Isao Shimizu, Haruo Mamyouda, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Large-scale general-purpose testers have been used for testing VLSI chips. They do not contribute directly to reduction of test cost because of their high operating cost. Test cost reduction has mainly been achieved by applying various techniques, such as multi-site testing. We have developed a low power on-board reconfigurable tester using an FPGA chip mounted on the board. The reconfigurable tester described in this paper can replace some of tester resources in general-purpose testers. The tester proposed can be configured by high-level HDL description derived from a tester language or a test program. With comparison to general-purpose testers, the proposed tester can provide a lower cost tester, resulting in reducing overall chip test cost. It also accomplishes lower power consumption, that is 1/100, providing an eco-friendly tester. Moreover, having the characteristic of being reconfigurable, our tester can be applied to product verifications in the design stage. We also report on its application to HDD Motor Driver Combo 1C. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | VLSI test / ATE / reconfigurable tester / on-board tester / low-power tester |
Paper # | DC2003-94 |
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Conference Information | |
Committee | DC |
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Conference Date | 2004/2/13(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
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Paper Information | |
Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Proposal of Low Power Board-Type Reconfigurable Tester |
Sub Title (in English) | |
Keyword(1) | VLSI test |
Keyword(2) | ATE |
Keyword(3) | reconfigurable tester |
Keyword(4) | on-board tester |
Keyword(5) | low-power tester |
1st Author's Name | Masayuki Sato |
1st Author's Affiliation | INNOTECH Corp.() |
2nd Author's Name | Hiroyuki Itabashi |
2nd Author's Affiliation | Graduate Shool of Engineering, Tokyo Metropolitan University |
3rd Author's Name | Nobuyuki Otsuka |
3rd Author's Affiliation | Renesas Technology Corp. |
4th Author's Name | Yasuro Kobayashi |
4th Author's Affiliation | Renesas Technology Corp. |
5th Author's Name | Osamu Muto |
5th Author's Affiliation | Renesas Technology Corp. |
6th Author's Name | Masayuki AraI |
6th Author's Affiliation | Renesas Technology Corp. |
7th Author's Name | Satoshi Fukumoto |
7th Author's Affiliation | Renesas Technology Corp. |
8th Author's Name | Kazuhiko Iwasaki |
8th Author's Affiliation | Renesas Technology Corp. |
9th Author's Name | Koji Uehara |
9th Author's Affiliation | Renesas Technology Corp. |
10th Author's Name | Isao Shimizu |
10th Author's Affiliation | Renesas Technology Corp. |
11th Author's Name | Haruo Mamyouda |
11th Author's Affiliation | Renesas Technology Corp. |
Date | 2004/2/13 |
Paper # | DC2003-94 |
Volume (vol) | vol.103 |
Number (no) | 668 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |