Presentation 2004/2/13
Dataflow Oriented Template Generation for Instruction-Based Self-Test of Processor Cores
kazuko KAMBE, Michiko INOUE, Hideo FUJlWARA,
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Abstract(in English) This paper presents a method of template generation for instruction-based self-test of processor cores. Our self-test methodology is based on hierarchical test generation. A test program template is an instruction sequence with unspecified operands, justifies test patterns from primary input to a module under test (MUT), and propagates resulting errors from MUT to primary output. Our proposed method constructs a sequence of instructions considering dependence of data flow between registers. We also consider the input space of MUT that can be justified by templates. Our method can generate multiple templates that cover different input spaces, and therefore, different detectable fault sets.
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Keyword(in English) template generation / instruction-based self-test / hierarchical test generation / data flow / dependence
Paper # DC2003-95
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Conference Date 2004/2/13(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Dataflow Oriented Template Generation for Instruction-Based Self-Test of Processor Cores
Sub Title (in English)
Keyword(1) template generation
Keyword(2) instruction-based self-test
Keyword(3) hierarchical test generation
Keyword(4) data flow
Keyword(5) dependence
1st Author's Name kazuko KAMBE
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City()
2nd Author's Name Michiko INOUE
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City
3rd Author's Name Hideo FUJlWARA
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City
Date 2004/2/13
Paper # DC2003-95
Volume (vol) vol.103
Number (no) 668
Page pp.pp.-
#Pages 6
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