| Presentation | 2004/2/13 A DFT Selection Method for Reducing Test Application Time of System-on-Chips Masahide MIYAZAKI, Toshinori HOSOKAWA, Hiroshi DATE, Michiaki MURAOKA, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes an SoC test architecture generation framework. It contains a database which stores the test cost information on several DFTs for every core, and DFT selection part which performs DFT selection for test cost minimization using this database in the early phase of the design flow. Moreover, the DFT selection problem is formulated and the algorithm which solves this is proposed. Experimental results showed that bottlenecks in test application time when using the single DFT method for all cores is reduced by performing DFT selection from several DFTs. As a result, the whole test application time is drastically shortened. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test scheduling / test access mechanism / wrapper / design for test |
| Paper # | DC2003-100 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2004/2/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A DFT Selection Method for Reducing Test Application Time of System-on-Chips |
| Sub Title (in English) | |
| Keyword(1) | test scheduling |
| Keyword(2) | test access mechanism |
| Keyword(3) | wrapper |
| Keyword(4) | design for test |
| 1st Author's Name | Masahide MIYAZAKI |
| 1st Author's Affiliation | STARC() |
| 2nd Author's Name | Toshinori HOSOKAWA |
| 2nd Author's Affiliation | Mathematical Information Engineering, Nihon University |
| 3rd Author's Name | Hiroshi DATE |
| 3rd Author's Affiliation | STARC |
| 4th Author's Name | Michiaki MURAOKA |
| 4th Author's Affiliation | STARC |
| 5th Author's Name | Hideo FUJIWARA |
| 5th Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology (NAIST) |
| Date | 2004/2/13 |
| Paper # | DC2003-100 |
| Volume (vol) | vol.103 |
| Number (no) | 668 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |