| Presentation | 2004/2/13 Input Temporal Spatial Constraint of Controller for Instruction-Based Self-Testing of Processor Cores Naotaka HOASHI, Kazuko KAMBE, Michiko INOUE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Instruction based self test is getting much attention as testing methodology of large-scale and high-speed processors. In the test generation methodology based on the hierarchical test generation, the gate-level test generation for each module and the generation of instruction sequence that justifies the test sequence and observes the test response for the module are performed. We consider the justifiable input space of the module as the constraint for test generation. In this paper, we propose input temporal spatial constraints as constraints for the test generation for sequential modules such as controllers. We compare test generation for controllers using the input temporal spatial constraints and conventional input spatial constraint, and show the necessity for input temporal spatial constraints. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Processor / Self-Testing / Test Program / Hierarchical Test Generation / Controller / Input Temporal Spatial Constraint |
| Paper # | DC2003-96 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2004/2/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Input Temporal Spatial Constraint of Controller for Instruction-Based Self-Testing of Processor Cores |
| Sub Title (in English) | |
| Keyword(1) | Processor |
| Keyword(2) | Self-Testing |
| Keyword(3) | Test Program |
| Keyword(4) | Hierarchical Test Generation |
| Keyword(5) | Controller |
| Keyword(6) | Input Temporal Spatial Constraint |
| 1st Author's Name | Naotaka HOASHI |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Kazuko KAMBE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Michiko INOUE |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 4th Author's Name | Hideo FUJIWARA |
| 4th Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2004/2/13 |
| Paper # | DC2003-96 |
| Volume (vol) | vol.103 |
| Number (no) | 668 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |