Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:M3-2
Session:
Number:M3-2-2
A Built-in Test Circuit to Monitor Changing Process of Resistive Open Defects in 3D ICs
Masashi Okamoto, Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume, Shyue-Kung Lu ,
pp.295-298
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
A resistive open defect in a 3D IC may change into a hard open one after shipping to a market. In this paper, a built-in test circuit is proposed to monitor the changing process of resisitive open defects occurring at interconnects between dies including an IEEE 1149.1 test circuit. Feasibility of the process monitor with the test circuit is examined by Spice simulation The simulation results show that the process of a resistive open defect can be monitored at a test speed of 1MHz per an interconnect.