Information and Systems-Dependable Computing(Date:2014/11/19)

Presentation
表紙

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[Date]2014/11/19
[Paper #]
目次

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[Date]2014/11/19
[Paper #]
プロセッサ設計自動化技術と医療機器への応用(フェロー就任記念講演,デザインガイア2014-VLSI設計の新しい大地-)

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[Date]2014/11/19
[Paper #]Vol.2014-SLDM-168 No.10
Investigation of the area reduction of observation part and control part in TSV fault detection circuit

Youhei MIYAMOTO,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  

[Date]2014/11/19
[Paper #]VLD2014-72,DC2014-26
Analytical placement consistent with hierarchical structure constraints in analog floorplan

Shigetoshi NAKATAKE,  

[Date]2014/11/19
[Paper #]VLD2014-73,DC2014-27
An efficient calculation of RTN-induced SRAM failure probability

Hiromitsu AWANO,  Masayuki HIROMOTO,  Takashi SATO,  

[Date]2014/11/19
[Paper #]VLD2014-74,DC32014-28
General-Purpose Pattern Recognition Processor Based on the k Nearest-Neighbor Algorithm with High-Speed, Low-Power

Shogo YAMASAKI,  Toshinobu AKAZAWA,  Fengwei AN,  Hans Jurgen MATTAUSCH,  

[Date]2014/11/19
[Paper #]VLD2014-75,DC2014-29
An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System

Masaharu YAMAMOTO,  Anh-Tuan HOANG,  Tetsushi KOIDE,  

[Date]2014/11/19
[Paper #]VLD2014-76,DC2014-30
Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification

Kouki SUGI,  Tetsushi KOIDE,  Anh-Tuan HOANG,  Takumi OKAMOTO,  Tatsuya SHIMIZU,  Toru TAMAKI,  Bisser Raytchev,  Kazufumi KANEDA,  Yoko KOMINAMI,  Shigeto YOSHIDA,  Shinji TANAKA,  

[Date]2014/11/19
[Paper #]VLD2014-77,DC2014-31
Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images

Takumi OKAMOTO,  Tetsushi KOIDE,  Anh-Tuan HOANG,  Koki SUGI,  Tatsuya SHIMIZU,  Toru TAMAKI,  Bisser RAYCHEV,  Kazuhumi KANEDA,  Yoko KOMINAMI,  Shigeto YOSHIDA,  Shinji TANAKA,  

[Date]2014/11/19
[Paper #]VLD2014-78,DC2014-32
Design of Flip-Flop with Timing Error Tolerance

Taito SUZUKI,  Youhua SHI,  Nozomu TOGAWA,  Kimiyoshi USAMI,  Masao YANAGISAWA,  

[Date]2014/11/19
[Paper #]VLD2014-79,DC2014-33
Data Dependent Optimization using Suspicious Timing Error Predictio for Reconfigurable Approximation Circuits

Kazushi KAWAMURA,  Shinya ABE,  Youhua SHI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2014/11/19
[Paper #]VLD2014-80,DC2014-34
An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations

Shinnosuke YOSHIDA,  Youhua SHI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2014/11/19
[Paper #]VLD2014-81,DC2014-35
A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture

ATSUSHI IWATA,  HIDEKI TAKASE,  KAZUYOSHI TAKAGI,  NAOFUMI TAKAGI,  

[Date]2014/11/19
[Paper #]Vol.2014-SLDM-168 No.4
割込みハンドラのハードウェア化を実現するシステムレベル設計手法(組み込みハードウエア,デザインガイア2014-VLSI設計の新しい大地-)

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[Date]2014/11/19
[Paper #]Vol.2014-SLDM-168 No.5
システムレベル設計における制御システム向けプロファイル機構(組み込みハードウエア,デザインガイア2014-VLSI設計の新しい大地-)

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[Date]2014/11/19
[Paper #]Vol.2014-SLDM-168 No.6
A hardware description method and sematics providing a timing constrant

Shunji NISHIMURA,  Motoki AMAGASAKI,  Toshinori SUEYOSHI,  

[Date]2014/11/19
[Paper #]VLD2014-82,DC2014-36
Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework

Junki KAWAGUCHI,  Yukihide KOHIRA,  

[Date]2014/11/19
[Paper #]VLD2014-83,DC2014-37
Voltage Dependence of Single Event Transient Pulses on 65nm Silicon-on-Thin-BOX and Bulk processes

Eiji SONEZAKI,  Kuiyuan ZHANG,  Jun FURUTA,  Kazutoshi KOBAYASHI,  

[Date]2014/11/19
[Paper #]VLD2014-84,DC2014-38
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs

Koichi FUJIWARA,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2014/11/19
[Paper #]VLD2014-85,DC2014-39
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