Presentation 2014-11-26
General-Purpose Pattern Recognition Processor Based on the k Nearest-Neighbor Algorithm with High-Speed, Low-Power
Shogo YAMASAKI, Toshinobu AKAZAWA, Fengwei AN, Hans Jurgen MATTAUSCH,
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Abstract(in English) A learning and pattern recognition processors for the k nearest neighbor (k-NN) recognition algorithm using a nearest Euclidean-distance search associative memory and a classification circuit for the k nearest neighbors. A SoC design example of the complete k-NN system is implemented in 180nm CMOS with 32 reference vectors and 2~8 classes. Small silicon area of 3.51 mm^2, low power consumption of 5.02mW and a maximum operating frequency of 42.9MHz (at V_
=1.8V) are achieved, Compared to implementation in software, the chip operates with a factor 1000 better energy efficiency.
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Keyword(in English) associative memory / Euclidean distance / k-NN / pattern matching / pattern recognition
Paper # VLD2014-75,DC2014-29
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Committee DC
Conference Date 2014/11/19(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) General-Purpose Pattern Recognition Processor Based on the k Nearest-Neighbor Algorithm with High-Speed, Low-Power
Sub Title (in English)
Keyword(1) associative memory
Keyword(2) Euclidean distance
Keyword(3) k-NN
Keyword(4) pattern matching
Keyword(5) pattern recognition
1st Author's Name Shogo YAMASAKI
1st Author's Affiliation Research Institute for Nanodevice and Bio Systems, Hiroshima University()
2nd Author's Name Toshinobu AKAZAWA
2nd Author's Affiliation Research Institute for Nanodevice and Bio Systems, Hiroshima University
3rd Author's Name Fengwei AN
3rd Author's Affiliation Research Institute for Nanodevice and Bio Systems, Hiroshima University
4th Author's Name Hans Jurgen MATTAUSCH
4th Author's Affiliation Research Institute for Nanodevice and Bio Systems, Hiroshima University
Date 2014-11-26
Paper # VLD2014-75,DC2014-29
Volume (vol) vol.114
Number (no) 329
Page pp.pp.-
#Pages 6
Date of Issue