| Presentation | 2014-11-26 Investigation of the area reduction of observation part and control part in TSV fault detection circuit Youhei MIYAMOTO, Hiroyuki YOTSUYANAGI, Masaki HASHIZUME, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fault detection circuit considering the effects of adjacent TSVs. However, the previous detection circuit requires to add a FF for each TSV to select a target TSV. Therefore, the method results in large area overhead. In addition, the relation of resolution and circuit area of VDL(Vernier Delay Line) used as a delay detection circuit has not been evaluated. In this study, in order to decrease circuit area of the TSV fault detection circuit, we improved the control part using BSC(Boundary Scan Cell). In addition, we also evaluate the most suitable number of delay gates in the VDL for small circuit area. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | TSV(Through-Silicon-Via) / design for testability / delay fault / VDL(Vernier-Delay-Line) |
| Paper # | VLD2014-72,DC2014-26 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2014/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Investigation of the area reduction of observation part and control part in TSV fault detection circuit |
| Sub Title (in English) | |
| Keyword(1) | TSV(Through-Silicon-Via) |
| Keyword(2) | design for testability |
| Keyword(3) | delay fault |
| Keyword(4) | VDL(Vernier-Delay-Line) |
| 1st Author's Name | Youhei MIYAMOTO |
| 1st Author's Affiliation | Graduate School of Advanced Technology and Science, Univ.of Tokushima() |
| 2nd Author's Name | Hiroyuki YOTSUYANAGI |
| 2nd Author's Affiliation | Institute of Technology and Science, Univ. of Tokushima |
| 3rd Author's Name | Masaki HASHIZUME |
| 3rd Author's Affiliation | Institute of Technology and Science, Univ. of Tokushima |
| Date | 2014-11-26 |
| Paper # | VLD2014-72,DC2014-26 |
| Volume (vol) | vol.114 |
| Number (no) | 329 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |