| Presentation | 2014/11/19 A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture ATSUSHI IWATA, HIDEKI TAKASE, KAZUYOSHI TAKAGI, NAOFUMI TAKAGI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, single instruction set heterogeneous multi-core architecture have focused attention for use in embedded systems. In order to reduce energy consumption on this architecture, while guaranteeing the deadline constraints of embedded real-time systems, appropriate task scheduling, including task allocation, dynamic voltage frequency scaling (DVFS) and selecting active cores, is necessary. In this paper, we propose a task migration method for real-time systems on single instruction set heterogeneous multi-core architecture. In the proposed method, DVFS algorithms for real-times systems are utilized for deciding whether tasks should be eventually migrated or not. The task migration method performs load balancing between cores and preferential use of energy efficient cores simultaneously, which leads to the reduction of energy consumption. We evaluated the amount of energy savings of the proposed method by simulating a task scheduling process. The results show that our method can save about 10.4% energy consumption in the best case compared to the existing DVFS method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Embedded Systems / Task Migration / Heterogeneous Multi-Cores / Energy Reduction |
| Paper # | Vol.2014-SLDM-168 No.4 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2014/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture |
| Sub Title (in English) | |
| Keyword(1) | Embedded Systems |
| Keyword(2) | Task Migration |
| Keyword(3) | Heterogeneous Multi-Cores |
| Keyword(4) | Energy Reduction |
| 1st Author's Name | ATSUSHI IWATA |
| 1st Author's Affiliation | Kyoto University() |
| 2nd Author's Name | HIDEKI TAKASE |
| 2nd Author's Affiliation | Kyoto University |
| 3rd Author's Name | KAZUYOSHI TAKAGI |
| 3rd Author's Affiliation | Kyoto University |
| 4th Author's Name | NAOFUMI TAKAGI |
| 4th Author's Affiliation | Kyoto University |
| Date | 2014/11/19 |
| Paper # | Vol.2014-SLDM-168 No.4 |
| Volume (vol) | vol.114 |
| Number (no) | 329 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |