| Presentation | 2014-11-26 An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations Shinnosuke YOSHIDA, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error correction techniques are strongly required. Suspicious timing error prediction (STEP) predicts timing errors by monitoring checkpoints by STEP circuits (STEPCs) and how to insert checkpoints is very important. We have proposed a network-flow-based checkpoint insertion algorithm for STEP. However, our algorithm may ignore long paths and insert checkpoints near the output. In this paper, we improve how to ignore short paths and set labels by estimating path lengths. Then, we can ignore only short paths and insert checkpoints into near the center of all long paths. We evaluate our algorithm by applying it to four benchmark circuits. Experimental results show that our proposed algorithm realizes an average of 1.71X overclocking compared with just inserting no STEPC. Furthermore, our improved algorithm realizes an average of 1.15X overclocking compared with our original algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Timing error prediction / robust design / delay variation / overclocking |
| Paper # | VLD2014-81,DC2014-35 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2014/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations |
| Sub Title (in English) | |
| Keyword(1) | Timing error prediction |
| Keyword(2) | robust design |
| Keyword(3) | delay variation |
| Keyword(4) | overclocking |
| 1st Author's Name | Shinnosuke YOSHIDA |
| 1st Author's Affiliation | Dept. of Conputer Science and Communications Engineering, Waseda University() |
| 2nd Author's Name | Youhua SHI |
| 2nd Author's Affiliation | Waseda Institute for Advanced Study, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Conputer Science and Communications Engineering, Waseda University |
| 4th Author's Name | Nozomu TOGAWA |
| 4th Author's Affiliation | Dept. of Conputer Science and Communications Engineering, Waseda University |
| Date | 2014-11-26 |
| Paper # | VLD2014-81,DC2014-35 |
| Volume (vol) | vol.114 |
| Number (no) | 329 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |