| Presentation | 2014-11-26 A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi FUJIWARA, Masao YANAGISAWA, Nozomu TOGAWA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image processing and computerized stock tradings. With recent process scaling in FPGAs, interconnection delays become dominant in total circuit delays nevertheless I/O buffers and wire buffers are provided and each FPGA has a different interconnection delay characteristics. We need to consider interconnection delays based on interconnection delay characteristics in FPGA designs. In this paper, we propose a floorplan-aware high-level synthesis algorithm utilizing interconnection delay characteristics targeting FPGA designs. Our target architecture is HDR, one of distributed-register architectures, and then we can estimate interconnection delays correctly by utilizing interconnection delay characteristics in an FPGA chip. Further, we reduce multiplexers generated and also limit the total number of inputs to multiplexers in HLS process. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 6% compared with our previous approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-level synthesis (HLS) / FPGA / floorplan / interconnection delay |
| Paper # | VLD2014-85,DC2014-39 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2014/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis (HLS) |
| Keyword(2) | FPGA |
| Keyword(3) | floorplan |
| Keyword(4) | interconnection delay |
| 1st Author's Name | Koichi FUJIWARA |
| 1st Author's Affiliation | Grad. of Computer Science and Communications Engineering, Waseda University() |
| 2nd Author's Name | Masao YANAGISAWA |
| 2nd Author's Affiliation | Grad. of Computer Science and Communications Engineering, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Grad. of Computer Science and Communications Engineering, Waseda University |
| Date | 2014-11-26 |
| Paper # | VLD2014-85,DC2014-39 |
| Volume (vol) | vol.114 |
| Number (no) | 329 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |