IEICE Technical Committee

Electronics-Silicon Devices and Materials(Date:2009/06/17)

Presentation

Strain effects in van der Pauw (VDP) stress sensor fabricated on (111) silicon in electronic packages

C.-H. Cho, H.-Y Cha,

[Date]2009/6/17
[Paper #]ED2009-88,SDM2009-83

Study on Quantum Electro-Dynamics in Vertical MOSFET

Masakazu Muraguchi, Tetsuo Endoh,

[Date]2009/6/17
[Paper #]ED2009-89,SDM2009-84

Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET

Tetsuo Endoh, Koji Sakui, Yukio Yasuda,

[Date]2009/6/17
[Paper #]ED2009-90,SDM2009-85

Lateral liquid-phase epitaxy of Ge on insulator using Si seed for ultrahigh speed transistor

T. Sadoh, T. Tanaka, Y. Ohta, K. Toko, M. Miyao,

[Date]2009/6/17
[Paper #]ED2009-91,SDM2009-86

Random Telegraph Signals in Two-Dimensional Array of Si Quantum Dots

Katsunori Makihara, Mitsuhisa Ikeda, Akira Kawanami, Seiichi Miyazaki,

[Date]2009/6/17
[Paper #]ED2009-92,SDM2009-87

Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot

Masakazu Muraguchi, Yukihiro Takada, Shintaro Nomura, Testuo Endoh, Kenji Shiraishi,

[Date]2009/6/17
[Paper #]ED2009-93,SDM2009-88

Fabrication of double-dot single-electron transistor in silicon nanowire

Mingyu Jo, Takuya Kaizawa, Masashi Arita, Akira Fujiwara, Yukinori Ono, Hiroshi Inokawa, Jung-Bum Choi, Yasuo Takahashi,

[Date]2009/6/17
[Paper #]ED2009-94,SDM2009-89

Future High Density Memory with Vertical Structured Device Technology

Tetsuo Endoh,

[Date]2009/6/17
[Paper #]ED2009-95,SDM2009-90

Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory

Yoon Kim, Seongjae Cho, Jang-Gn Yun, Il Han Park, Gil Sung Lee, Doo-Hyun Kim, Dong Hua Li, Se Hwan Park, Wandong Kim, Wonbo Shim, Byung-Gook Park,

[Date]2009/6/17
[Paper #]ED2009-96,SDM2009-91

Architecture and verification of the row chain cell array for polymer random access memory

J. H. Kim, C. Y. Ahn, S. S. Lee,

[Date]2009/6/17
[Paper #]ED2009-97,SDM2009-92

Enhancement of the programming speed in SANOS nonvolatile memory device designed utilizing Al_2O_3 and SiO_2 stacked tunneling layers

H. W. Kim, D. H. Kim, J. H. You, T. W. Kim,

[Date]2009/6/17
[Paper #]ED2009-98,SDM2009-93

Novel Capacitorless DRAM Cell for Low Voltage Operation and Long Data Retention Time

Woojun Lee, Woo Young Choi,

[Date]2009/6/17
[Paper #]ED2009-99,SDM2009-94

Multilevel dual-channel NAND flash memories with high read and program verifying speeds utilizing asymmetrically-doped channel regions

J. W. Lee, J. H. You, S. H. Jang, K. D. Kwack, T. W. Kim,

[Date]2009/6/17
[Paper #]ED2009-100,SDM2009-95

Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices

Seongjae Cho, Jung Hoon Lee, Yun Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park,

[Date]2009/6/17
[Paper #]ED2009-101,SDM2009-96

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奥付

[Date]2009/6/17
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