| Presentation | 2009-06-26 Multilevel dual-channel NAND flash memories with high read and program verifying speeds utilizing asymmetrically-doped channel regions J. W. Lee, J. H. You, S. H. Jang, K. D. Kwack, T. W. Kim, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NAND flash memory / multilevel dual-channel / high-speed multilevel reading / current sensing / high-speed program verifying |
| Paper # | ED2009-100,SDM2009-95 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2009/6/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Multilevel dual-channel NAND flash memories with high read and program verifying speeds utilizing asymmetrically-doped channel regions |
| Sub Title (in English) | |
| Keyword(1) | NAND flash memory |
| Keyword(2) | multilevel dual-channel |
| Keyword(3) | high-speed multilevel reading |
| Keyword(4) | current sensing |
| Keyword(5) | high-speed program verifying |
| 1st Author's Name | J. W. Lee |
| 1st Author's Affiliation | Division of Electronics and Computer Engineering, Hanyang University() |
| 2nd Author's Name | J. H. You |
| 2nd Author's Affiliation | Division of Electronics and Computer Engineering, Hanyang University |
| 3rd Author's Name | S. H. Jang |
| 3rd Author's Affiliation | Department of Nanoscale Semiconductor Engineering, Hanyang University |
| 4th Author's Name | K. D. Kwack |
| 4th Author's Affiliation | Division of Electronics and Computer Engineering, Hanyang University |
| 5th Author's Name | T. W. Kim |
| 5th Author's Affiliation | Division of Electronics and Computer Engineering, Hanyang University:Department of Nanoscale Semiconductor Engineering, Hanyang University |
| Date | 2009-06-26 |
| Paper # | ED2009-100,SDM2009-95 |
| Volume (vol) | vol.109 |
| Number (no) | 98 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |