Presentation 2009-06-26
Novel Capacitorless DRAM Cell for Low Voltage Operation and Long Data Retention Time
Woojun Lee, Woo Young Choi,
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Abstract(in English) A capacitorless dynamic random access memory (DRAM) cell is proposed for low voltage operation with device scaling-down. The proposed DRAM cell features low body doping concentration and recessed gate. Low doping body is introduced to use punch-through as a program mechanism. Punch-through occurs easily in the case of low doping body concentration. Therefore low doping body allows high speed operation in spite of low operation voltage. However low doping body leads to severe drain induced barrier lowering (DIBL). DIBL reduces data retention time. Recessed gate structure can suppress DIBL and increase data retention time. Finally, The proposed capacitorless DRAM cell has long data retention time and operates with low operating voltage.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) low voltage / retention time / capacitorless DRAM / recessed gate / low doping body
Paper # ED2009-99,SDM2009-94
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Conference Information
Committee SDM
Conference Date 2009/6/17(1days)
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Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Novel Capacitorless DRAM Cell for Low Voltage Operation and Long Data Retention Time
Sub Title (in English)
Keyword(1) low voltage
Keyword(2) retention time
Keyword(3) capacitorless DRAM
Keyword(4) recessed gate
Keyword(5) low doping body
1st Author's Name Woojun Lee
1st Author's Affiliation Dept. of Electronic Eng., Sogang Univ.()
2nd Author's Name Woo Young Choi
2nd Author's Affiliation Dept. of Electronic Eng., Sogang Univ.
Date 2009-06-26
Paper # ED2009-99,SDM2009-94
Volume (vol) vol.109
Number (no) 98
Page pp.pp.-
#Pages 4
Date of Issue