Presentation 2009-06-26
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Yoon Kim, Seongjae Cho, Jang-Gn Yun, Il Han Park, Gil Sung Lee, Doo-Hyun Kim, Dong Hua Li, Se Hwan Park, Wandong Kim, Wonbo Shim, Byung-Gook Park,
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Abstract(in English) The 3-dimensional folded NAND array having vertical channels has a large integration density and reliable memory characteristics without short channel effect. But, this kind of 3-D memory with vertical channels experiences inevitable interference between cells on both sides of a single silicon pillar, which is called PCI (Paired Cell Interference). As the thickness of silicon fin is scaled down, this phenomenon becomes severer. Consequently, the PCI is a crucial scaling restriction factor of vertical type flash memory. In this paper, we propose a multi-level reading method which utilizes PCI.
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Keyword(in English) NAND flash memory / 3-D array / PCI (Paired Cell Interference)
Paper # ED2009-96,SDM2009-91
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Committee SDM
Conference Date 2009/6/17(1days)
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Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Sub Title (in English)
Keyword(1) NAND flash memory
Keyword(2) 3-D array
Keyword(3) PCI (Paired Cell Interference)
1st Author's Name Yoon Kim
1st Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University()
2nd Author's Name Seongjae Cho
2nd Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
3rd Author's Name Jang-Gn Yun
3rd Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
4th Author's Name Il Han Park
4th Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
5th Author's Name Gil Sung Lee
5th Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
6th Author's Name Doo-Hyun Kim
6th Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
7th Author's Name Dong Hua Li
7th Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
8th Author's Name Se Hwan Park
8th Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
9th Author's Name Wandong Kim
9th Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
10th Author's Name Wonbo Shim
10th Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
11th Author's Name Byung-Gook Park
11th Author's Affiliation Inter-university Semiconductor Research Center:School of Electrical Engineering, Seoul National University
Date 2009-06-26
Paper # ED2009-96,SDM2009-91
Volume (vol) vol.109
Number (no) 98
Page pp.pp.-
#Pages 4
Date of Issue