| Presentation | 2009-06-26 Enhancement of the programming speed in SANOS nonvolatile memory device designed utilizing Al_2O_3 and SiO_2 stacked tunneling layers H. W. Kim, D. H. Kim, J. H. You, T. W. Kim, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The programming characteristics of polysilicon-aluminum oxide-nitride-oxide-silicon (SANOS) nonvolatile memory devices with Al_2O_3 and SiO_2 stacked tunneling layers were investigated. The electron and hole drifts in the Si_3N_4 layer were calculated to determine the program speed of the proposed SANOS devices by using the two band model taking into account Shockley-Reed statistics for the trap population, the continuity equation for the charge transport, and the Poisson equation for the electric field. Simulation results showed that enhancement of the programming speed in polysilicon-oxide-nitride-oxide-silicon was achieved by utilizing SiO_2 and Al_2O_3 stacked tunneling layers and the top Al_2O_3 blocking layer. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SANOS / SONOS / charge transport / silicon nitride / stacked tunneling layer |
| Paper # | ED2009-98,SDM2009-93 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2009/6/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Enhancement of the programming speed in SANOS nonvolatile memory device designed utilizing Al_2O_3 and SiO_2 stacked tunneling layers |
| Sub Title (in English) | |
| Keyword(1) | SANOS |
| Keyword(2) | SONOS |
| Keyword(3) | charge transport |
| Keyword(4) | silicon nitride |
| Keyword(5) | stacked tunneling layer |
| 1st Author's Name | H. W. Kim |
| 1st Author's Affiliation | Department of Nanoscale Semiconductor Engineering, Hanyang University() |
| 2nd Author's Name | D. H. Kim |
| 2nd Author's Affiliation | Division of Electronics and Computer Engineering, Hanyang University |
| 3rd Author's Name | J. H. You |
| 3rd Author's Affiliation | Division of Electronics and Computer Engineering, Hanyang University |
| 4th Author's Name | T. W. Kim |
| 4th Author's Affiliation | Department of Nanoscale Semiconductor Engineering, Hanyang University:Division of Electronics and Computer Engineering, Hanyang University |
| Date | 2009-06-26 |
| Paper # | ED2009-98,SDM2009-93 |
| Volume (vol) | vol.109 |
| Number (no) | 98 |
| Page | pp.pp.- |
| #Pages | 3 |
| Date of Issue | |