Presentation 2009-06-26
Architecture and verification of the row chain cell array for polymer random access memory
J. H. Kim, C. Y. Ahn, S. S. Lee,
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Abstract(in English) A polymer memory, that is considered as one of the next-generation nonvolatile memories, has various excellent electrical and mechanical properties such as small cell feature sizes, high density integrations, and mass-producibility. Although the polymer memories have important advantages for reliability, the peripheral circuits of the polymer memories have not been studied yet, thereby not many research articles available. In this paper, we analyzed and simulate the row chain cell array structure as cross-point cell scheme and demonstrated its ability to correctly read data and reduce noise between cells. Also we using the CMOS 0.35μm process, we verified and simulated with test result for the row chain cell array.
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Keyword(in English) polymer memory / nonvolatile memory / leakage current
Paper # ED2009-97,SDM2009-92
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Committee SDM
Conference Date 2009/6/17(1days)
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Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Architecture and verification of the row chain cell array for polymer random access memory
Sub Title (in English)
Keyword(1) polymer memory
Keyword(2) nonvolatile memory
Keyword(3) leakage current
1st Author's Name J. H. Kim
1st Author's Affiliation Electronics and Computer Engineering, Hanyang University()
2nd Author's Name C. Y. Ahn
2nd Author's Affiliation Electronics and Computer Engineering, Hanyang University
3rd Author's Name S. S. Lee
3rd Author's Affiliation Electronics and Computer Engineering, Hanyang University
Date 2009-06-26
Paper # ED2009-97,SDM2009-92
Volume (vol) vol.109
Number (no) 98
Page pp.pp.-
#Pages 4
Date of Issue