Presentation 2009-06-26
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Seongjae Cho, Jung Hoon Lee, Yun Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) During the programming operation of the NAND-type flash memory array, the program-inhibited cell is biased with positive voltages on the source and drain (S/D) junctions while program voltage is applied on the word-line (WL), which enables the self-boosting of Si channel potential to avoid unwanted program operation. As the device is aggressively scaled down and the channel doping concentration is increased accordingly, the couplings among WL, floating gate or storage node, and Si channel which are crucial factor in the self-boosting scheme should be investigated more thoroughly. In this work, the dependence of channel potential self-boosting on the channel length and doping concentration in 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-Si is investigated by numerical device simulation. Since there is seldom feasible ways of measuring the channel potential by physical probing, series of simulation works are thought to offer insightful results.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) NAND-type flash memory / program inhibition / self-boosting / FinFET / device simulation
Paper # ED2009-101,SDM2009-96
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Committee SDM
Conference Date 2009/6/17(1days)
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Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Sub Title (in English)
Keyword(1) NAND-type flash memory
Keyword(2) program inhibition
Keyword(3) self-boosting
Keyword(4) FinFET
Keyword(5) device simulation
1st Author's Name Seongjae Cho
1st Author's Affiliation Inter-university Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University()
2nd Author's Name Jung Hoon Lee
2nd Author's Affiliation Inter-university Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University
3rd Author's Name Yun Kim
3rd Author's Affiliation Inter-university Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University
4th Author's Name Jang-Gn Yun
4th Author's Affiliation Inter-university Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University
5th Author's Name Hyungcheol Shin
5th Author's Affiliation Inter-university Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University
6th Author's Name Byung-Gook Park
6th Author's Affiliation Inter-university Semiconductor Research Center (ISRC):School of Electrical Engineering and Computer Science, Seoul National University
Date 2009-06-26
Paper # ED2009-101,SDM2009-96
Volume (vol) vol.109
Number (no) 98
Page pp.pp.-
#Pages 4
Date of Issue