Best Paper Award

Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits[IEICE TRANS. FUNDAMENTALS, VOL.E102–A, NO.12 DECEMBER 2019]

Ryosuke MATSUO
Ryosuke MATSUO
Jun SHIOMI
Jun SHIOMI
Tohru ISHIHARA
Tohru ISHIHARA
Hidetoshi ONODERA
Hidetoshi ONODERA
Akihiko SHINYA
Akihiko SHINYA
Masaya NOTOMI
Masaya NOTOMI

Because of the continuously growing demand for computing power and the limit of performance improvement by the process of shrinking electric integrated circuits, novel computing methods have been studied hard. Optical circuits are one such method and have been gaining attention again because of their ultra-high performance. This paper proposes new optimization methods for an existing design method for optical logic circuits based on Binary Decision Diagrams (BDD). In the existing method, a logic function is represented by a multi-terminal BDD to manage multiple values and each node of the minimized shared-BDD is converted into a Directional Coupler (DC) element which behaves as a selector of optical beams with respect to a control signal, but the shared node is then converted into a splitter of optical beams requiring that the enlarged input beam and the reduced number of nodes does not relate to the reduced size and power. This paper introduces a Wavelength Division Multiplexing (WDM) method for several optical beams to implement several logic functions in one circuit, and a conversion method of a splitter to DC or a tree of DC’s for shared nodes. Sharing a circuit by WDM is effective to reduce the number of DC’s and the power consumption, and the elimination of splitters contributes to power reduction with the cost of DC’s. Three optimization methods are introduced: Ad-hoc, Minimum area and Minimum power, and these are applied to a 7-3 parallel counter and a 4-bit multiplier. Minimum area minimizes the number of DC’s and Minimum power optimizes the power consumption by reducing the splitters with DC’s. There is a trade-off between the number of DC’s and the power consumption. Ad-hoc cares about both the number of DC’s and the power consumption and reduces the power to 1/6.8 on the parallel counter with the same number of DC’s compared with the straightforward implementation of Shared-BDD and reduces the power to 1/2.8 with half the number of DC’s on the multiplier. The improvement of the algorithm caring about delays and computerization is expected in the future.