Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2015/02/23)

Presentation
A Length Matching Routing Method for Disordered Pins in PCB Design

Ran Zhang,  Tieyuan Pan,  Li Zhu,  Takahiro Watanabe,  

[Date]2015/2/23
[Paper #]VLD2014-171
Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design

Jun SHIOMI,  Tohru ISHIHARA,  Hidetoshi ONODERA,  

[Date]2015/2/23
[Paper #]VLD2014-172
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories

Masashi TAWADA,  Shinji KIMURA,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2015/2/23
[Paper #]VLD2014-173
Physical Unclonable Function Using RTN-Induced Time-Dependent Frequency Variance in Ring Oscillators

Motoki YOSHINAGA,  Hiromitsu AWANO,  Masayuki HIROMOTO,  Takashi SATO,  

[Date]2015/2/23
[Paper #]VLD2014-174
On PLL Layouts Evaluation based on Transistor-array Style

Yuki MIURA,  Atsushi NANRI,  Qing DONG,  Shigetoshi NAKATAKE,  

[Date]2015/2/23
[Paper #]VLD2014-175
Ground Bounce Suppressive Effect using Power Switch Driver to control Power Switch Rise Time

Tetsutaro OHNISHI,  Kimiyoshi USAMI,  

[Date]2015/2/23
[Paper #]VLD2014-176
Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design

Atsushi ITO,  Makoto IKEDA,  

[Date]2015/2/23
[Paper #]VLD2014-177
LSI implementation of FEC for high-speed optical transmission

Koji MIYANOHANA,  Susumu HIRANO,  Hideo YOSHIDA,  Yoshikuni MIYATA,  Kenya SUGIHARA,  Kazuo KUBO,  Yoshiaki KONISHI,  Kiyoshi ONOHARA,  Noriyuki MINEGISHI,  Takashi SUGIHARA,  

[Date]2015/2/23
[Paper #]VLD2014-178
Energy minimization by voltage choice targeted for logic synthesis in silicon on thin buried oxide

Jun KAWASAKI,  Kimiyoshi USAMI,  

[Date]2015/2/23
[Paper #]VLD2014-179
A Parallel Algorithm for Realizing the Lax-Friedrichs Scheme in Computational Fluid Dynamics and its FPGA Implementation

Yusuke HAGA,  Shinobu NAGAYAMA,  Shin'ichi WAKABAYASHI,  Masato INAGI,  

[Date]2015/2/23
[Paper #]VLD2014-180
An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework

Satoshi OTSUKI,  Atsushi TAKAHASHI,  

[Date]2015/2/23
[Paper #]VLD2014-181
A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists

Masaru OYA,  Youhua SHI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2015/2/23
[Paper #]VLD2014-182
Implementation and Evaluation of Architecture Using Lookup Table for Approximate Computing

Shoichiro Sugiyama,  Ahmed Tanvir,  Yuko Hara-Azumi,  

[Date]2015/2/23
[Paper #]VLD2014-183
List-sheduling for tasks with execution time variation

Komei NOMURA,  Yasuhiro TAKASHIMA,  

[Date]2015/2/23
[Paper #]VLD2014-184
複写される方へ

,  

[Date]2015/2/23
[Paper #]
Reprographic Reproduction outside Japan

,  

[Date]2015/2/23
[Paper #]
奥付

,  

[Date]2015/2/23
[Paper #]
裏表紙

,  

[Date]2015/2/23
[Paper #]
<<12 21-38hit(38hit)