| Presentation | 2015-03-04 An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework Satoshi OTSUKI, Atsushi TAKAHASHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the current typical of integrated circuits, the performance is determined by the maximum delay between flip-flops. Therfore, the reduction of the maximum delay has been pursured, however, it approaches the limit. In the circuits with the error detection/correction system, the performance is bounded by the clock period and delay error rate. In this paper, we discuss a relation between clock period and delay error rate on a circuit which has high error rate. We evaluate the performance of variable-latency circuit of a multiplier with error-detection/correction system on FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | error-detection/correction system / clock period / delay error rate / multiplier |
| Paper # | VLD2014-181 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework |
| Sub Title (in English) | |
| Keyword(1) | error-detection/correction system |
| Keyword(2) | clock period |
| Keyword(3) | delay error rate |
| Keyword(4) | multiplier |
| 1st Author's Name | Satoshi OTSUKI |
| 1st Author's Affiliation | Tokyo Institute of Technology() |
| 2nd Author's Name | Atsushi TAKAHASHI |
| 2nd Author's Affiliation | Tokyo Institute of Technology |
| Date | 2015-03-04 |
| Paper # | VLD2014-181 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |