Presentation	2015-03-04 Energy minimization by voltage choice targeted for logic synthesis in silicon on thin buried oxide Jun KAWASAKI, Kimiyoshi USAMI,
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Abstract(in English)	Silicon on Thin Buried Oxide (SOTB) technology enables us to reduce supply voltage because the Vth variation can be suppressed. Therefore, SOTB can work with the wider range of the voltage than the bulk transistor. However, on the SOTB design it is necessary that the logic synthesis correspond to the cell performance changed by the wide voltage range. In this paper, we clarify the energy smallest voltage intended for by logic synthesis by analyzing the circuits which changed the supply voltages.
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Keyword(in English)	ultra low voltage operation / silicon on thin buried oxide / logic synthesis
Paper #	VLD2014-179
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Committee	VLD
Conference Date	2015/2/23(1days)
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Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
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Title (in English)	Energy minimization by voltage choice targeted for logic synthesis in silicon on thin buried oxide
Sub Title (in English)
Keyword(1)	ultra low voltage operation
Keyword(2)	silicon on thin buried oxide
Keyword(3)	logic synthesis
1st Author's Name	Jun KAWASAKI
1st Author's Affiliation	Graduate School of Engineering and Science, Shibaura Institute of Technology()
2nd Author's Name	Kimiyoshi USAMI
2nd Author's Affiliation	Department of Information Science and Engineering, Shibaura Institute of Technology
Date	2015-03-04
Paper #	VLD2014-179
Volume (vol)	vol.114
Number (no)	476
Page	pp.pp.-
#Pages	6
Date of Issue