| Presentation | 2015-03-03 Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of microprocessors. This paper shows architectural-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we show several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28-nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Near-threshold computing / Statistical static timing analysis (SSTA) |
| Paper # | VLD2014-172 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design |
| Sub Title (in English) | |
| Keyword(1) | Near-threshold computing |
| Keyword(2) | Statistical static timing analysis (SSTA) |
| 1st Author's Name | Jun SHIOMI |
| 1st Author's Affiliation | Graduate School of Informatics, Kyoto University() |
| 2nd Author's Name | Tohru ISHIHARA |
| 2nd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 3rd Author's Name | Hidetoshi ONODERA |
| 3rd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| Date | 2015-03-03 |
| Paper # | VLD2014-172 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |