| Presentation | 2015-03-03 A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories Masashi TAWADA, Shinji KIMURA, Masao YANAGISAWA, Nozomu TOGAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | non-volatile memory / bit-write reduction / energy reduction / write-reduction code / error-correctin code |
| Paper # | VLD2014-173 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories |
| Sub Title (in English) | |
| Keyword(1) | non-volatile memory |
| Keyword(2) | bit-write reduction |
| Keyword(3) | energy reduction |
| Keyword(4) | write-reduction code |
| Keyword(5) | error-correctin code |
| 1st Author's Name | Masashi TAWADA |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Shinji KIMURA |
| 2nd Author's Affiliation | Graduate School of Infomation, Production and Systems, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Electronic and Photonic Systems, Waseda University |
| 4th Author's Name | Nozomu TOGAWA |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2015-03-03 |
| Paper # | VLD2014-173 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 115 |
| Date of Issue | |