| Presentation | 2015-03-04 Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design Atsushi ITO, Makoto IKEDA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inherent robustness. However design flow for the circuit have not been automated. We investigated data flow in the loop circuit on self-synchronous circuits to clarify the constraint for sequential circuit on self-synchronous circuit. We proposed a method of optimization of sequential circuit in self-synchronous circuits design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | gate-level pipeline / self synchronous / automated design |
| Paper # | VLD2014-177 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design |
| Sub Title (in English) | |
| Keyword(1) | gate-level pipeline |
| Keyword(2) | self synchronous |
| Keyword(3) | automated design |
| 1st Author's Name | Atsushi ITO |
| 1st Author's Affiliation | The Univ. of Tokyo() |
| 2nd Author's Name | Makoto IKEDA |
| 2nd Author's Affiliation | The Univ. of Tokyo |
| Date | 2015-03-04 |
| Paper # | VLD2014-177 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
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