| Presentation | 2015-03-04 On PLL Layouts Evaluation based on Transistor-array Style Yuki MIURA, Atsushi NANRI, Qing DONG, Shigetoshi NAKATAKE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that unit-transistors of the same size form an array. It contributes to an easy implementation of design automation, and it also serves a design to mitigate the process variability in 90nm beyond. In this work, utilizing a phase locked loop(PLL) circuit as a motif, we verify the relationship between the fine processes and TA-style. We generate the layouts of the PLL based on the TA-style on 0.6μm, 180nm, 65nm in three processes, and compare them with respect to the area and the post-layout simulation results of the control voltage of the VCO. Besides, we also generate a custom layout in 0.6μm process, and fabricate the chip. We report the compare resut with the TA-style one. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Analog layout / Phase locked loop / Transistor array |
| Paper # | VLD2014-175 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On PLL Layouts Evaluation based on Transistor-array Style |
| Sub Title (in English) | |
| Keyword(1) | Analog layout |
| Keyword(2) | Phase locked loop |
| Keyword(3) | Transistor array |
| 1st Author's Name | Yuki MIURA |
| 1st Author's Affiliation | Graduate School of Environmental Engineering, The University of Kitakyushu() |
| 2nd Author's Name | Atsushi NANRI |
| 2nd Author's Affiliation | Graduate School of Environmental Engineering, The University of Kitakyushu |
| 3rd Author's Name | Qing DONG |
| 3rd Author's Affiliation | Graduate School of Environmental Engineering, The University of Kitakyushu |
| 4th Author's Name | Shigetoshi NAKATAKE |
| 4th Author's Affiliation | Graduate School of Environmental Engineering, The University of Kitakyushu |
| Date | 2015-03-04 |
| Paper # | VLD2014-175 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |