Electronics-Integrated Circuits and Devices(Date:1997/10/16)

Presentation
表紙

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[Date]1997/10/16
[Paper #]
目次

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[Date]1997/10/16
[Paper #]
A Low-Power Design Methodology utilizing dual supply Voltages and Power Analysis

Masahiro Kanazawa,  Kimiyoshi Usami,  Mutsunori Igarashi,  Takashi Ishikawa,  Kazutaka Nogami,  

[Date]1997/10/16
[Paper #]ICD97-150-158
Adaptive Code-Book Encoding for Low Power Chip-Interface

Satoshi Komatsu,  Makoto Ikeda,  Kunihiro Asada,  

[Date]1997/10/16
[Paper #]ICD97-150-158
A Charge-Transfer-Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's

Shoichiro Kawashima,  Toshihiko Mori,  Ryuhei Sasagawa,  Makoto Hamaminato,  Shigetoshi Wakayama,  Kazuo Sukegawa,  Isao Fukushi,  

[Date]1997/10/16
[Paper #]ICD97-150-158
A Complementary Half-Swing Bus Architecture and its Application for Wide Band SRAM Macro

Yasunobu Nakase,  Atsushi Iwabu,  Harufusa Kondo,  Koichiro Mashiko,  Yoshio Matsuda,  Takeshi Tokuda,  

[Date]1997/10/16
[Paper #]ICD97-150-158
A 250-MHz Operation 0.25-μm 1-Mb SRAM Macrocell

Nobutaro SHIBATA,  

[Date]1997/10/16
[Paper #]ICD97-150-158
A 500MHz 4Mb CMOS Pipeline-Burst Cache SRAM

Koichi Takeda,  Kazuyuki Nakamura,  Hideo Toyoshima,  Kenji Noda,  Hiroaki Ohkubo,  Tetsuya Uchida,  Toshiyuki Shimizu,  Toshiro Itani,  Ken Tokashiki,  Koji Kishimoto,  

[Date]1997/10/16
[Paper #]ICD97-150-158
Design of a 1.8V-only NAND Flash Memory

Toru Tanzawa,  Tomoharu Tanaka,  Ken Takeuchi,  Hiroshi Nakamura,  

[Date]1997/10/16
[Paper #]ICD97-150-158
Practical Low Power Design Architecture for 256Mb DRAM

M. Kinoshita,  T. Tanizaki,  T. Fujino,  M. Tsukude,  K. Arimoto,  

[Date]1997/10/16
[Paper #]ICD97-150-158
Circuit Design Technique for Multi-giga-bit DRAMs

K. Arimoto,  

[Date]1997/10/16
[Paper #]ICD97-150-158
[OTHERS]

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[Date]1997/10/16
[Paper #]