| Presentation | 1997/10/16 A 500MHz 4Mb CMOS Pipeline-Burst Cache SRAM Koichi Takeda, Kazuyuki Nakamura, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A secondary cache SRAM is an indispensable CPU partner in a high-performance system. The main objectives are 1) pipeline-burst operation, 2) 32b 500MHz (2GB/s) I/Os, and 3) point-to-point communication with a CPU, as well as shortened latency and reduced noise and power caused by high-speed, high-bandwidth I/O operation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Cache / SRAM / High-speed / Interface / Bandwidth |
| Paper # | ICD97-150-158 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/10/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 500MHz 4Mb CMOS Pipeline-Burst Cache SRAM |
| Sub Title (in English) | |
| Keyword(1) | Cache |
| Keyword(2) | SRAM |
| Keyword(3) | High-speed |
| Keyword(4) | Interface |
| Keyword(5) | Bandwidth |
| 1st Author's Name | Koichi Takeda |
| 1st Author's Affiliation | Silicon Systems Research Labs.() |
| 2nd Author's Name | Kazuyuki Nakamura |
| 2nd Author's Affiliation | Silicon Systems Research Labs. |
| 3rd Author's Name | Hideo Toyoshima |
| 3rd Author's Affiliation | Silicon Systems Research Labs. |
| 4th Author's Name | Kenji Noda |
| 4th Author's Affiliation | ULSI Device Development Labs. |
| 5th Author's Name | Hiroaki Ohkubo |
| 5th Author's Affiliation | ULSI Device Development Labs. |
| 6th Author's Name | Tetsuya Uchida |
| 6th Author's Affiliation | ULSI Device Development Labs. |
| 7th Author's Name | Toshiyuki Shimizu |
| 7th Author's Affiliation | Second LSI Memory Div., NEC Corporation |
| 8th Author's Name | Toshiro Itani |
| 8th Author's Affiliation | ULSI Device Development Labs. |
| 9th Author's Name | Ken Tokashiki |
| 9th Author's Affiliation | ULSI Device Development Labs. |
| 10th Author's Name | Koji Kishimoto |
| 10th Author's Affiliation | ULSI Device Development Labs. |
| Date | 1997/10/16 |
| Paper # | ICD97-150-158 |
| Volume (vol) | vol.97 |
| Number (no) | 318 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |