Presentation	1997/10/16 Circuit Design Technique for Multi-giga-bit DRAMs K. Arimoto,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	This paper describes amulti giga bit DRAM technologies focused on circuit design. Process and device technique less than 0.15um induce some kind of problems to achieve high performance DRAM. To solve these problems, key circuits design technique have been introduced as follows. Sense amplifire circuits and low Vth transistor logic with power management are useful for high spped at low voltage. Long data retaintion cuircuit technique good for mobile equipments is required. Additionally, testability, redundancy and new device structure DRAM are presented. These circuit technologies will provide not only multi giga bit DRAM but also multi media system LSI near future.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Giga bit DRAM / High speed low power DRAM / Multi function DRAM / SOI DRAM
Paper #	ICD97-150-158
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Conference Information
Committee	ICD
Conference Date	1997/10/16(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Circuit Design Technique for Multi-giga-bit DRAMs
Sub Title (in English)
Keyword(1)	Giga bit DRAM
Keyword(2)	High speed low power DRAM
Keyword(3)	Multi function DRAM
Keyword(4)	SOI DRAM
1st Author's Name	K. Arimoto
1st Author's Affiliation	ULSI Lab. Mitsubishi Electric Corp.()
Date	1997/10/16
Paper #	ICD97-150-158
Volume (vol)	vol.97
Number (no)	318
Page	pp.pp.-
#Pages	7
Date of Issue