Presentation 1997/10/16
A Low-Power Design Methodology utilizing dual supply Voltages and Power Analysis
Masahiro Kanazawa, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Kazutaka Nogami,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper describes a low-power design methodology utilizing dual supply voltages. Both of the original supply voltage VDDH and a reduced supply voltage VDDL are used in a core of an LSI for reducing power. By making non-critical paths operate at VDDL, power reduction can be achieved keeping high performance. Key components of this methodology are a synthesis CAD tool of the structure with dual supply voltages and an automatic layout technique. We applied the methodology to random logic parts of a media processor Mpact^. Through the power analysis, we have found that the power is reduced by 56% at the part to which we applied the methodology and by 31% at the core of the chip.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low-Power / dual supply voltages / random logic / media processor / CAD
Paper # ICD97-150-158
Date of Issue

Conference Information
Committee ICD
Conference Date 1997/10/16(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Low-Power Design Methodology utilizing dual supply Voltages and Power Analysis
Sub Title (in English)
Keyword(1) Low-Power
Keyword(2) dual supply voltages
Keyword(3) random logic
Keyword(4) media processor
Keyword(5) CAD
1st Author's Name Masahiro Kanazawa
1st Author's Affiliation Semiconductor Division, TOSHIBA Corp.()
2nd Author's Name Kimiyoshi Usami
2nd Author's Affiliation Semiconductor Division, TOSHIBA Corp.
3rd Author's Name Mutsunori Igarashi
3rd Author's Affiliation Semiconductor Division, TOSHIBA Corp.
4th Author's Name Takashi Ishikawa
4th Author's Affiliation Semiconductor Division, TOSHIBA Corp.
5th Author's Name Kazutaka Nogami
5th Author's Affiliation Semiconductor Division, TOSHIBA Corp.
Date 1997/10/16
Paper # ICD97-150-158
Volume (vol) vol.97
Number (no) 318
Page pp.pp.-
#Pages 8
Date of Issue