Presentation	1997/10/16 A 250-MHz Operation 0.25-μm 1-Mb SRAM Macrocell Nobutaro SHIBATA,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Design techniques for mega-bit-class size-configurable SRAM macrocells are described. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells are employed with via-hole programming in address decoder. A new squashed memory-cell layout for CMOS SRAM's is proposed to reduce the access time and power dissipation. To shorten the time for writing data, writing buffers are connected to bitlines without multiplexer. Also, read-out circuitry using current-mode sense amplifiers is mentioned. A 1-Mb SRAM test chip was fabricated with a 0.25-μm bulk-CMOS process. The SRAM has demonstrated 250-MHz operation and 145-mW power dissipation at a 2.5-V typical power supply.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	SRAM / macrocell / size configurable / current-mode sense amplifier
Paper #	ICD97-150-158
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Conference Information
Committee	ICD
Conference Date	1997/10/16(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A 250-MHz Operation 0.25-μm 1-Mb SRAM Macrocell
Sub Title (in English)
Keyword(1)	SRAM
Keyword(2)	macrocell
Keyword(3)	size configurable
Keyword(4)	current-mode sense amplifier
1st Author's Name	Nobutaro SHIBATA
1st Author's Affiliation	NTT System Electronics Laboratories()
Date	1997/10/16
Paper #	ICD97-150-158
Volume (vol)	vol.97
Number (no)	318
Page	pp.pp.-
#Pages	8
Date of Issue