| Presentation | 1997/10/16 Practical Low Power Design Architecture for 256Mb DRAM M. Kinoshita, T. Tanizaki, T. Fujino, M. Tsukude, K. Arimoto, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a new circuit design architecture whitch is effective for low power, and high speed DRAMs. The characteristics of this schemes are: 1) a fsih bone layout of the sub-decode-line in the divided word line (DWL) architecture, 2) a hierachicalbit line (BL) precharge power line and and 3) a non-reset row block control. A 256Mb DRAM using these techniques was fabricated by a 0.25um CMOS process. An extremely low standby current (23uA) and self refresh current (607uA) were obtained. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DRAM / divided word line / fish bone layout / self refresh |
| Paper # | ICD97-150-158 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 1997/10/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Practical Low Power Design Architecture for 256Mb DRAM |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | divided word line |
| Keyword(3) | fish bone layout |
| Keyword(4) | self refresh |
| 1st Author's Name | M. Kinoshita |
| 1st Author's Affiliation | ULSI Lab. Mitsubishi Electric Corp.() |
| 2nd Author's Name | T. Tanizaki |
| 2nd Author's Affiliation | ULSI Lab. Mitsubishi Electric Corp. |
| 3rd Author's Name | T. Fujino |
| 3rd Author's Affiliation | ULSI Lab. Mitsubishi Electric Corp. |
| 4th Author's Name | M. Tsukude |
| 4th Author's Affiliation | ULSI Lab. Mitsubishi Electric Corp. |
| 5th Author's Name | K. Arimoto |
| 5th Author's Affiliation | ULSI Lab. Mitsubishi Electric Corp. |
| Date | 1997/10/16 |
| Paper # | ICD97-150-158 |
| Volume (vol) | vol.97 |
| Number (no) | 318 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |