Information and Systems-Dependable Computing(Date:2012/06/15)

Presentation
表紙

,  

[Date]2012/6/15
[Paper #]
目次

,  

[Date]2012/6/15
[Paper #]
正誤表

,  

[Date]2012/6/15
[Paper #]
An evaluation of a don't care filling method to improve fault sensitization coverage

Ryosuke WAKASUGI,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2012/6/15
[Paper #]DC2012-9
A Reduction Technique of Input Sequences for Time-Multiplexed On-Chip Path Delay Measurement Using Embedded Delay Measurement Circuit

Kentaroh KATOH,  

[Date]2012/6/15
[Paper #]DC2012-10
A Study on Fault Tolerant Test Pattern Generators for Reliable Built-in Self Test

Yuki FUKAZAWA,  Tsuyoshi IWAGAKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2012/6/15
[Paper #]DC2012-11
Empirical study for signal integrity-defects

Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Toshiyuki TSUTSUMI,  Kouji YAMAZAKI,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  

[Date]2012/6/15
[Paper #]DC2012-12
Note on Layout-Aware High Accuracy Estimation of Bridge/Open Fault Coverage

Masayuki Arai,  Yoshihiro Shimizu,  Kazuhiko Iwasaki,  

[Date]2012/6/15
[Paper #]DC2012-13
An Evaluation of Low Power BIST Method

Yasuo SATO,  Senling WANG,  Takaaki KATO,  Kohei MIYASE,  Seiji KAJIHARA,  

[Date]2012/6/15
[Paper #]DC2012-14
On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing

Yuta YAMATO,  Tomokazu YONEDA,  Kazumi HATAYAMA,  Michiko INOUE,  

[Date]2012/6/15
[Paper #]DC2012-15
Evaluation of the on-chip temperature and voltage using ring-oscillator-based monitoring circuit and a study for an application to field test

Yousuke MIYAKE,  Takuma SASAKAWA,  Yasuo SATO,  Seiji KAJIHARA,  Yukiya MIURA,  

[Date]2012/6/15
[Paper #]DC2012-16
複写される方へ

,  

[Date]2012/6/15
[Paper #]
Notice for Photocopying

,  

[Date]2012/6/15
[Paper #]
奥付

,  

[Date]2012/6/15
[Paper #]
裏表紙

,  

[Date]2012/6/15
[Paper #]