Presentation	2012-06-22 A Reduction Technique of Input Sequences for Time-Multiplexed On-Chip Path Delay Measurement Using Embedded Delay Measurement Circuit Kentaroh KATOH,
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Abstract(in English)	Time-multiplexed delay measurement is useful for the reduction of the measurement time of the on-chip delay measurement using embedded delay measurement circuit. However this approach requires extra input sequences for scan shift clock control between measurements and the selection of the end points of the measured paths. These sequences become data overhead. Therefore, the data volume of these extra input sequences should be as small as possible. This paper proposes a reduction technique of the whole input sequences with the reduction of the two input sequences. The volume of input sequence for scan shift clock control between measurements is reduced considering the number of the shift clocks between measurements. The volume of the input sequence for the selection of the end points of the measured paths is reduced by the continuous measurement of the paths with the identical end points. The evaluation shows that the volume of the input sequence for scan shift clock control is 72.6% of the conventional one. The volume of the input sequence for the selection of the end points of the measured paths is 32.2% of the conventional one. The whole input sequence is 82.2% of the conventional one.
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Keyword(in English)	time-multiplexed delay measurement / on-chip delay measurement / input sequence for shift clock control / input sequence for path selection
Paper #	DC2012-10
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Committee	DC
Conference Date	2012/6/15(1days)
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Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Reduction Technique of Input Sequences for Time-Multiplexed On-Chip Path Delay Measurement Using Embedded Delay Measurement Circuit
Sub Title (in English)
Keyword(1)	time-multiplexed delay measurement
Keyword(2)	on-chip delay measurement
Keyword(3)	input sequence for shift clock control
Keyword(4)	input sequence for path selection
1st Author's Name	Kentaroh KATOH
1st Author's Affiliation	Department of Electrical Engineering, Tsuruoka National College of Technology()
Date	2012-06-22
Paper #	DC2012-10
Volume (vol)	vol.112
Number (no)	102
Page	pp.pp.-
#Pages	7
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